Field effect transistors (FETs) are the basic building block of today's integrated circuit. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates.
State of the art metal oxide semiconductor (MOS) transistors are fabricated by depositing a gate stack material over a gate dielectric and a substrate. Generally, the MOS transistor fabrication process implements lithography and etching processes to define the conductive, e.g., poly-Si, gate structures. The gate structure and substrate are thermally oxidized, and, after this, source/drain extensions are formed by implantation. Sometimes the implant is performed using a spacer to create a specific distance between the gate and the implanted junction. In some instances, such as in the manufacture of an n-FET device, the source/drain extensions for the n-FET device are implanted with no spacer. For a p-FET device, the source/drain extensions are typically implanted with a spacer present. A thicker spacer is typically formed after the source/drain extensions have been implanted. The deep source/drain implants are then performed with the thick spacer present. High temperature anneals are performed to activate the junctions after which the source/drain and top portion of the gate are generally silicided. Silicide formation typically requires that a refractory metal be deposited on a Si-containing substrate followed by a process to produce the silicide material. The silicide process forms low resistivity contacts to the deep source/drain regions and the gate conductor.
High integration density can reduce manufacturing costs. In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find a way to further downscale the dimensions of field effect transistors (FETs), such as metal oxide semiconductors. The downscaling of transistor dimensions allows for improved performance as well as compactness, but such downscaling has some device and yield degrading effects.
With continuing scaling down of the transistor size, it is required that the size of the via contacts also decreases. It is, however, difficult to etch contact vias and to avoid gate-to-via shorts when the size of the via opening is small and spacing between gates and vias is small. Although thin contact area stressed layers make it easier for etching the via opening, such thin contact area stressed layers reduce the stress transferred into the channel of the transistor. This degrades the performance of the transistor and, as such, is highly undesirable. The gate-to-via shorts reduce chip yields and then increase the costs for IC manufacturing.
In addition to the above, another key challenge in fabricating high performance semiconductor structures is to reduce the external parasitic source/drain (S/D) resistance. Typically, an epitaxial raised S/D is implemented to address this problem. However, the epitaxial raised S/D process adds significant device integration complexity. The pre-epitaxial surface cleans and epitaxial growth conditions are sensitive to the underlying doping species present in the semiconductor substrate and their concentration and require extensive optimization.
In view of the above, there is a need for providing a semiconductor structure that has improved device performance as a result of a stressed channel region without increasing the size of the contact vias. Moreover, there is also a need for providing a semiconductor structure having improved device performance in with the external parasitic S/D resistance is reduced without the need of epitaxially growing a raised S/D semiconductor region. To reduce area penalty due to lithography misalignment, it is desirable to have vias self-aligned to gates.